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Honored Contributor[DE2 Board]If Sram is to be acessed both by NIOS and another Avalon Master Component
Hi,
I am creating a Avalon-MM-Master component that is able to read data from and write data to SRAM chip. In the design SRAM is slave to both CPU and the Avalon master component. After compiling the top level design and downloading it to the DE2 board, I try to run simple C application(just printing a string on the terminal ) under NIOSII IDE. However, NIOSII IDE report the following error: Downloading 00080000 ( 0%) Downloaded 53KB in 0.8s (66.2KB/s) Verifying 00080000 ( 0%) Verify failed between address 0x80000 and 0x8D287 Leaving target processor paused When I remove the newly created Avalon-MM-Master component from the system (in SOPC) program can run normally. So the problem is related to the new component. My guess is : since both CPU and the new component has the right to access SRAM, it may cause conflict. So does anybody have experience related to this issue? Can "flow control" or Avalon tristate Mater solve this problem?4 Replies
Altera_ForumI would brake the debugging in seperate steps. At first debug your connection to the sram. Which sram device you are uing? May be you could use the SOPC tristate bridge istead of your sram controller. (see example in C:\altera\91\nios2eds\examples\vhdl\niosII_cycloneII_2c35\standard)
After you have verified that programs can be executed from sram insert your Avalon MM master. Next verify the slave port of the master. Try to write and read back a control register. Than go on to verify master read and write. I had a short look over your code. Why you didn't decode the avs_byteenable signal in the csr process? Why are you using a 64-bit data port on the master? (access to memory is a 16-bit) How is the dataflow later in your application? (where gets the master the data from). Please explain your application more in detail may be I can help more. Jens- Altera_Forum
TO_BE_DONE
- Altera_Forum
Which SOPC component is between 0x80000 and 0x8D287 ? SRAM?
Disable rd and wr signals of your master and try running again. - Altera_Forum
Is your second Avalon master generating data during the upstart?
If that is the case you could build in an enable/disable function in this second master, controlled by action from the CPU after the upstart Just a thought...
