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Altera_Forum
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15 years ago

[DE2 Board]If Sram is to be acessed both by NIOS and another Avalon Master Component

Hi, I am creating a Avalon-MM-Master component that is able to read data from and write data to SRAM chip. In the design SRAM is slave to both CPU and the Avalon master component. After compil...
Altera_Forum's avatar
Altera_Forum
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15 years ago

Is your second Avalon master generating data during the upstart?

If that is the case you could build in an enable/disable function in this second master, controlled by action from the CPU after the upstart

Just a thought...