[DE2 Board]If Sram is to be acessed both by NIOS and another Avalon Master Component

I would brake the debugging in seperate steps. At first debug your connection to the sram. Which sram device you are uing? May be you could use the SOPC tristate bridge istead of your sram controller. (see example in C:\altera\91\nios2eds\examples\vhdl\niosII_cycloneII_2c35\standard)

After you have verified that programs can be executed from sram insert your Avalon MM master. Next verify the slave port of the master. Try to write and read back a control register. Than go on to verify master read and write.

I had a short look over your code. Why you didn't decode the avs_byteenable signal in the csr process? Why are you using a 64-bit data port on the master? (access to memory is a 16-bit) How is the dataflow later in your application? (where gets the master the data from).

Please explain your application more in detail may be I can help more.

Jens