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Honored Contributor
Honored ContributorDE2-115 SRAM Avalon Wrapper Problem
Hello,
I am using the DE2-115 board with 50 MHz clock coming from Y2 pin. I have written a Avalon Wrapper in VHDL for interfacing the SRAM chip (IS61WV102416BLL-10) and then set the timing parameters using the SOPC tool. However when I do a memory test on the SRAM in NIOS2 EDS, the reads are different from the writes. I can not communicate with the SRAM in a healthy fashion. I suspect that the timing parameters could be wrong. Has anyone been successful in implementing and testing their own SRAM controller to control the DE2-115's SRAM? Thanks in advance
