DE2-115 RS232 Configuration

Well, several comments.

1) use the code snippet tool to put your code inline. It is monospaced and scrolling and allows for us to actually read your code...

module RS232_Swtich_Test (input clk, input [7:0] data, output TxD);
    reg[4:0] bitcounter; // counts the number of bits that have been sent
    reg[31:0] counter; // counts the number of clock ticks, used to divide the internal clock
    reg[9:0] rightShiftReg;
 
    initial
        begin
        counter <= 0;
        bitcounter <= 0;
        end
 
    always @ (posedge clk)
        begin
        counter <= counter+1;
...
 

2) Your 'uart' has no way to synchronize the data input with its state; it is just free-running sending data continuously. You don't have any signals to tell it to start sending a new character, or when it is done sending a character and you can validly change the input data[7:0].

3) I assume input clock is 50MHz (since 9600*5208 = 49,996,800) but since you don't disclose how this module connects to the device pins it is hard to say it could work.

4) The initial value of rightShiftReg[] is undefined, and it does not get loaded until the first time bitcounter[] counts up to 9. So your first character transmitted is garbage.

5) When rightShiftReg[] gets shifted right, you should fill with a STOP bit value (1'b1') on the MSB. Right now you shift right and default zero fill the MSB.

All of these issues are likely to cause framing errors at best and just pure garbage at worst.

The RS232 interface on the DE2-115 is completely 'soft', meaning that the UART must be completely implemented in custom FPGA code. There is an on-board TTL to RS232 converter, but it is only a level shifting driver/receiver to the 9pin PC compatible connector.

So if you have a functioning UART implementation, and the baud rate (ie, 9600, 115200, etc) and data format (ie, 8N1) match it should work fine.

What code is in the FPGA, and how is it configured? It will make all the difference.

I have attached the code for the FPGA below. In LabVIEW I have it configured for 8 data bits, 1 stop bit, a baud rate of 9600, and odd parity.

Here is the verilog code in text:

module RS232_Swtich_Test(input clk, input [7:0] data, output TxD);

reg[4:0] bitcounter; // counts the number of bits that have been sent

// counts the number of clock ticks, used to divide the internal clock

reg[31:0] counter;

reg[9:0] rightShiftReg;

initial begin

counter <= 0;

bitcounter <= 0;

end

always @ (posedge clk) begin

counter <= counter+1;

if (counter >= 5208) begin // divides the clock for a Baud rate of 9600

counter <= 0;

bitcounter <= bitcounter+1;

rightShiftReg <= rightShiftReg>>1;

if (bitcounter >=9) begin

rightShiftReg <= {1'b1, data[7:0], 1'b0};

bitcounter <= 0;

end

end

end

assign TxD = rightShiftReg[0];

endmodule

Thank you for the feedback. This is my first time posting code so I didn't know about code snipping cools. I will use those from now on. I will get to work on those changes but out of curiosity how would this code work differently when being read through MATLAB rather than LabVIEW. I have run this exact code and been able to successfully read it in MATLAB before so why will it work in MATLAB but not in LabVIEW? Dose MATLAB use a different way to read than LABVIEW?

Don't know, I don't use either MATLAB or LABVIEW. probably depends on the operating system, too. TBH I really don't see how your posted code works at all, in practice, other that you just being lucky.

Hi ,

Thanks for this useful conversation. Please check the following tutorials on how to use LabView in programming FPGA. Actually we don't have certain support to this in this forums plus the LabView cannot compile the design code you have to use Intel compiler.

http://www.ni.com/tutorial/14532/en/

Regards,