DE2-115 RS232 Configuration

I have attached the code for the FPGA below. In LabVIEW I have it configured for 8 data bits, 1 stop bit, a baud rate of 9600, and odd parity.

Here is the verilog code in text:

module RS232_Swtich_Test(input clk, input [7:0] data, output TxD);

reg[4:0] bitcounter; // counts the number of bits that have been sent

// counts the number of clock ticks, used to divide the internal clock

reg[31:0] counter;

reg[9:0] rightShiftReg;

initial begin

counter <= 0;

bitcounter <= 0;

end

always @ (posedge clk) begin

counter <= counter+1;

if (counter >= 5208) begin // divides the clock for a Baud rate of 9600

counter <= 0;

bitcounter <= bitcounter+1;

rightShiftReg <= rightShiftReg>>1;

if (bitcounter >=9) begin

rightShiftReg <= {1'b1, data[7:0], 1'b0};

bitcounter <= 0;

end

end

end

assign TxD = rightShiftReg[0];

endmodule