DE2-115 RS232 Configuration

Well, several comments.

1) use the code snippet tool to put your code inline. It is monospaced and scrolling and allows for us to actually read your code...

module RS232_Swtich_Test (input clk, input [7:0] data, output TxD);
    reg[4:0] bitcounter; // counts the number of bits that have been sent
    reg[31:0] counter; // counts the number of clock ticks, used to divide the internal clock
    reg[9:0] rightShiftReg;
 
    initial
        begin
        counter <= 0;
        bitcounter <= 0;
        end
 
    always @ (posedge clk)
        begin
        counter <= counter+1;
...
 

2) Your 'uart' has no way to synchronize the data input with its state; it is just free-running sending data continuously. You don't have any signals to tell it to start sending a new character, or when it is done sending a character and you can validly change the input data[7:0].

3) I assume input clock is 50MHz (since 9600*5208 = 49,996,800) but since you don't disclose how this module connects to the device pins it is hard to say it could work.

4) The initial value of rightShiftReg[] is undefined, and it does not get loaded until the first time bitcounter[] counts up to 9. So your first character transmitted is garbage.

5) When rightShiftReg[] gets shifted right, you should fill with a STOP bit value (1'b1') on the MSB. Right now you shift right and default zero fill the MSB.

All of these issues are likely to cause framing errors at best and just pure garbage at worst.