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Altera_Forum's avatar
Altera_Forum
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10 years ago

DE0-nano SPI slave device

Hello all,

I'm interfacing my DE0-nano with a micro-controller using SPI protocol. The FPGA is acting as a slave and the Micro-controller as a master.

All the input signals of the SPI (MOSI, SCLK, CS) are synchronised with the FPGA clock (100 MHz)

Everything is working fine with low SPI clocks.

Now i'm trying to increase the speed of the SPI(SCLK=5 MHz) but the MISO DATAs are shifted.

With my logic analyzer, I detect the problem. In fact, in the falling edge of the SPI clock , data on the MISO line should be ready before the the next rising edge of SPI clock.But it is not the case.

The time that the MISO data required after the falling edge of the SPI clock is about (0.125 us). So if i want to get high speed communication, i must reduce this delay.

I'd like to ask for help of the experts of community if there is a way to do that.

Kind Regards,

4 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    10 years ago

    One raw solution to fix your problem is shifting the clock or MISO signal inside the fpga.

    Another option is checking the SPI configuration on master or slave: usually spi controllers have Phase and Polarity settings which allow you to align serial data to the correct clock edges.
  • Altera_Forum's avatar
    Altera_Forum
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    10 years ago

    are you saying you saw there is a fix delay between at the first SS_N and SCLK?

  • Altera_Forum's avatar
    Altera_Forum
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    10 years ago

    I think Cris' 'raw' solution is the most elegant. Launch your MISO data back to the micro at a different point in the SCLK cycle. Assuming you're operating your spi slave module from the 100MHz clock, you have 20 different options (20 different 100HMz clock cycles in your target 5MHz SCLK speed) from which to launch the data. So, you can 'position' your MISO data, w.r.t. SCLK with 10ns accuracy.

    Cheers,

    Alex
  • Altera_Forum's avatar
    Altera_Forum
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    10 years ago

    Think you all for your answers.

    Sorry, i forget an important detail. In fact, i used adum3402 (4-channel digital isolators to convert 3v/5v and 5v/3v) to interface the FPGA board and the Micro-controller board.

    My problem comes from this circuit, the delay between the output signal form the Micro-controller and the input signal to FPGA is long, i.e. the SPI clock from the Micro-controller can arrive shifted by 180° to the FPGA when the speed is increased.

    I have to take another converter to minimize this delay.

    I'll let you know.

    Best regards,