Forum Discussion
3 Replies
- Altera_Forum
Honored Contributor
If you download Terasic's example there are already designs available, albeit on Verilog. I guess you'll have to do the translation to VHDL from there.
- Altera_Forum
Honored Contributor
--- Quote Start --- If you download Terasic's example there are already designs available, albeit on Verilog. I guess you'll have to do the translation to VHDL from there. --- Quote End --- Thanks alot!!! - Altera_Forum
Honored Contributor
--- Quote Start --- Thanks alot!!! --- Quote End --- But the problem is i'm not much familiar with verilog :(