Forum Discussion
Altera_Forum
Honored Contributor
9 years agoIf you download Terasic's example there are already designs available, albeit on Verilog. I guess you'll have to do the translation to VHDL from there.
If you download Terasic's example there are already designs available, albeit on Verilog. I guess you'll have to do the translation to VHDL from there.