Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
9 years ago

DDR3 RESET implementation overview

Dear Gurus, We are recently having invalid data when we reset our DDR3. Below there is Altera Documentation and my questions. We are using Quartus 11.1, with StratixIII-EP3SL70-F780C4 ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
8 years ago

1- Should we connect the power up reset input(Input of FPGA coming from PC to global reset_n? Yes

2- Should we use afi_reset_n output at all? Yes

3- Should we connect the afi_reset_n output of the FPGA to global reset_n not to soft reset_n because we want to reset the PLL it is out of lock? No

4- When should we use soft_reset_n, what is the advantage of using soft_reset_n, does it allow to recalibrate DDR3? Yes, you are right. It use to reset the memory.

5- Should we use calibration success or calibration fail in the reset routine? No, this signal to monitor the calibration stage.

Regards,

WaiMun

(This message was posted on behalf of Intel Corporation)