Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

DDR2-SDRAM High performance controller

Hi All,

I am currently using the DDR2-SDRAM High performance controller on Quartus II 8.0. I assume that the controller had been successfully generated. but i can not effectively test the the system as the example driver always hangs.

I have noticed using signal tap that the signal mem_local_rdata_valid never got asserted by the controller.

Does anyone have experience with this?

Thanks

Test conditions:

Stratix II EPS30F67

Micron's DDR2 MT47H16M16

Quartus II 8.0

Yems

11 Replies

Show More
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    16 years ago

    Hi Yems,

    I am not sure why rdata_valid signal is not being asserted. Altera has a very good simulation model that runs in ModelSim. I tested my design first with the simulation before compiling it for the hardware. I would suggest you to try the simulation and see if you get the same result. I have done most of my compilation/simulation with 9.1, so I am not sure if 8.0 has an issue with DDR2 controller.

    Kumaran