Forum Discussion
Altera_Forum
Honored Contributor
16 years agoHi Yems,
I am not sure why rdata_valid signal is not being asserted. Altera has a very good simulation model that runs in ModelSim. I tested my design first with the simulation before compiling it for the hardware. I would suggest you to try the simulation and see if you get the same result. I have done most of my compilation/simulation with 9.1, so I am not sure if 8.0 has an issue with DDR2 controller. Kumaran