Honored ContributorWhen I tried to fit my design into Cycleon II, I got an error message
Error: DQS I/O pin "ddr2_dqs[0]" does not feed a Clock Delay Control block I use Altera's DDR2 controller, why does this happen?
Honored ContributorI think, because your ddr2_dqs[0] signal is assigned to pin, which is not supports DQS mode.
Honored ContributorNo. You're getting this error because it is a DQS pin, and it is configured as a DQS pin. Quartus therefore expects it to drive a Clock Delay Control block, but it's not.
So... 1 - Make sure you've connected all your signals correctly to the DDR2 controller in your design. 2 - You're DDR2 controller isn't getting optimized away is it? If you haven't actually connected the write and read data path to something, the whole thing will get wiped out. JakeHonored ContributorI have a question dealing with DQS and Clock Delay Control block.
What if I need to make a zero delay DQS strobe... I use Altera DDR2 SDRAM controller on Cyclone II. I have a situations during DDR2 burst reading, when DQS comes much later then data on DQ lines. And when controller trigs DQ-data with delayed DQS I get data corruption. Is here is a possibility to get not delayed DQS strobe to trig data from DDR2 memory? Thank you.Honored ContributorWell, I'm not super familiar with Cyclone II but in other families you can instruct the controller that you want to instantiate the DLL externally. In which case you can manually control the DQS delay if you want to. I've done it on Stratix II but not Cyclone II.
JakeHonored ContributorI suppose, that Cyclone II not so flexible as Stratix II in way of DLL control . Anyway, thank you for reply.
I've solved my problem by adding a little delay on DQ inputs, which gave me reading errors.Honored ContributorHelo,
I also have the same problem but DQS fater than data, how can I change clock delay control in Cyclone2? can I use script command like this: set_instance_assignment -name DUAL_PURPOSE_CLOCK_PIN_DELAY -to <to> -entity <entity name> <value> Can anyone help me, I actually need the help! Thanks.Honored Contributorhello i have the same problem and couldnt make it work..
Honored ContributorI am having the same problem. I have the DSK kit which has the Cyclone 2 EP2C70F672C6 chip. It also has the Micron MT8HTF3264AY-40E; 256 Mbyte, 32 Mbyte x 64, 167 MHz, 1.8 V, 240-pin, non-ECC, un-buffered DDR2 SDRAM DIMM.
I am trying to R/W this dram by using the example design generated when using the DDR2 IP core. I don't what to use NIOS. I have assigned the pins according to the manual. The error message I get is: Error (172078): DQS I/O pin "ddr2_dqs[0]" does not feed a Clock Delay Control block Interestingly, I went to the Production Tests that were installed when I got the board. Once such test does test the DDR2 which passes. Unfortunately, Altera only gives the .sof file. There is also a NIOS "standard" design. However, if one looks at it the design is only using 16 bits for the DRAM. Rather worthless since it has 64 bits! So, I'm stuck as you are.
