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Altera_Forum's avatar
Altera_Forum
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17 years ago

ddr2 Delay Control block?

When I tried to fit my design into Cycleon II, I got an error message Error: DQS I/O pin "ddr2_dqs[0]" does not feed a Clock Delay Control block I use Altera's DDR2 controller, why does this ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

I suppose, that Cyclone II not so flexible as Stratix II in way of DLL control . Anyway, thank you for reply.

I've solved my problem by adding a little delay on DQ inputs, which gave me reading errors.