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Altera_Forum
Honored Contributor
Honored Contributorddr2 Delay Control block?
When I tried to fit my design into Cycleon II, I got an error message Error: DQS I/O pin "ddr2_dqs[0]" does not feed a Clock Delay Control block I use Altera's DDR2 controller, why does this ...
Altera_ForumHonored Contributor
Honored ContributorWell, I'm not super familiar with Cyclone II but in other families you can instruct the controller that you want to instantiate the DLL externally. In which case you can manually control the DQS delay if you want to. I've done it on Stratix II but not Cyclone II.
Jake
