Forum Discussion
Altera_Forum
Honored Contributor
Honored Contributorddr2 Delay Control block?
When I tried to fit my design into Cycleon II, I got an error message Error: DQS I/O pin "ddr2_dqs[0]" does not feed a Clock Delay Control block I use Altera's DDR2 controller, why does this ...
Altera_ForumHonored Contributor
Honored ContributorI have a question dealing with DQS and Clock Delay Control block.
What if I need to make a zero delay DQS strobe... I use Altera DDR2 SDRAM controller on Cyclone II. I have a situations during DDR2 burst reading, when DQS comes much later then data on DQ lines. And when controller trigs DQ-data with delayed DQS I get data corruption. Is here is a possibility to get not delayed DQS strobe to trig data from DDR2 memory? Thank you.
