ddr2_auto_verify_timing

Hi all,

I am using Altera' DDR2 IP core with feedback clock option and I am encountering one problem:

The auto_verify_ddr_timing.tcl script could not be done.

error: ddr timing cannot be verified until project has been successfully compiled.

error: evaluation of tcl script auto_verify_ddr_timing.tcl unsuccessful

I found the following information in DDR2_IP_extraction_log.txt:

error: evaluation of tcl script c:/altera/8.0/ip/ddr_ddr2_sdram/system_timing/tan_arg_dqsfbc.tcl unsuccessful

error: quartus ii classic timing analyzer was unsuccessful. 1 error, 2 warnings

error: peak virtual memory: 208 megabytes

error: processing ended: thu jun 04 12:03:50 2009

error: elapsed time: 00:00:21

error: total cpu time (on all processors): 00:00:21

assertion failed( $errmsg=="" ) $errmsg:{moving paennode failed: wanted doing_rd_delayed$ on node (reg) ddr2_ip dr2_ip_ddr_sdram|ddr2_ip_auk_ddr_sdram dr2_ip_auk_ddr_sdram_inst|ddr2_ip_auk_ddr_datapath:ddr_io|ddr2_ip_auk_ddr_dqs_group:\g_datapath:0:g_ddr_io|dq_enable_reset[0]

- asynch to soft_reset_reg2_n~clkctrl ic(0.679 ns) + cell(0.363 ns)

- synch to ddr2_ip:r2_ip_ddr_sdram|ddr2_ip_auk_ddr_sdram:\r2_ip_auk_ddr_sdram_inst|ddr2_ip_auk_ddr_datapath:ddr_io|ddr2_ip_auk_ddr_dqs_group:\g_datapath:0:g_ddr_io|dq_enable_reset[0]~feeder ic(0.000 ns) + cell(0.097 ns)

- clock to ddr_pll_fb_stratixii:g_stratixpll_ddr_fedback_pll_inst|altpll:altpll_component|_clk1~clkctrl ic(0.659 ns) + cell(0.378 ns)

- fanout to ddr2_ip-> r2_ip_ddr_sdram|ddr2_ip_auk_ddr_sdram->r2_ip_auk_ddr_sdram_inst|ddr2_ip_auk_ddr_datapath:ddr_io|ddr2_ip_auk_ddr_dqs_group:\g_datapath:0:g_ddr_io|dqs_io~regout reg ic(0.232 ns) + cell(0.372 ns)

\ located at lcff_x77_y50_n3}

assertion failed(false) delay unreasonable $k:sysclk_postctrl $v:0

------------------------------------------------

moving paennode failed: wanted doing_rd_delayed$ on node (reg) ddr2_ip->r2_ip_ddr_sdram|ddr2_ip_auk_ddr_sdram->r2_ip_auk_ddr_sdram_inst|ddr2_ip_auk_ddr_datapath:ddr_io|ddr2_ip_auk_ddr_dqs_group:\g_datapath:0:g_ddr_io|dq_enable_reset[0]

- asynch to soft_reset_reg2_n~clkctrl ic(0.679 ns) + cell(0.363 ns)

- synch to ddr2_ip->r2_ip_ddr_sdram|ddr2_ip_auk_ddr_sdram->r2_ip_auk_ddr_sdram_inst|ddr2_ip_auk_ddr_datapath:ddr_io|ddr2_ip_auk_ddr_dqs_group:\g_datapath:0:g_ddr_io|dq_enable_reset[0]~feeder ic(0.000 ns) + cell(0.097 ns)

- clock to ddr_pll_fb_stratixii:g_stratixpll_ddr_fedback_pll_inst|altpll:altpll_component|_clk1~clkctrl ic(0.659 ns) + cell(0.378 ns)

- fanout to ddr2_ip->r2_ip_ddr_sdram|ddr2_ip_auk_ddr_sdram->r2_ip_auk_ddr_sdram_inst|ddr2_ip_auk_ddr_datapath:ddr_io|ddr2_ip_auk_ddr_dqs_group:\g_datapath:0:g_ddr_io|dqs_io~regout reg ic(0.232 ns) + cell(0.372 ns)

\ located at lcff_x77_y50_n3

while executing

"error "$errmsg""

(procedure "::ddr::dqsfbc::extract_s2_paths" line 162)

invoked from within

"::ddr::dqsfbc::extract_s2_paths $node $variation_name extract_debug $settings_array(enable_postamble) "

invoked from within

"set res [::ddr::dqsfbc::extract_s2_paths $node $variation_name extract_debug $settings_array(enable_postamble) ]"

invoked from within

"foreach_in_collection node [get_timing_nodes -type pin] {

set node_name [get_timing_node_info -info name $node]

set res [::ddr::dqsfbc::extract_s2_pat..."

("foreach" body line 14)

invoked from within

"foreach pvt {fast slow} {

set dq_pin_list

[list]

set tco_min ""

set tco_max ""

set pincount 0

set clock_pins_found 0

catch { delete_timing_netlist }

i..."

invoked from within

"time {

set margins(capture) ""

set margins(resync1) ""

set margins(resync2) ""

set margins(postambleen) ""

set margins(postamble1) ""

set margins(post..."

invoked from within

"set t [time {

set margins(capture) ""

set margins(resync1) ""

set margins(resync2) ""

set margins(postambleen) ""

set margins(postamble1) ""

set margi..."

(file "c:/altera/8.0/ip/ddr_ddr2_sdram/system_timing/tan_arg_dqsfbc.tcl" line 156)

------------------------------------------------

I used the sample driver of IP not mine.

The proplem didn't occur while feedback clock is turn off.

Could anyone help me?

Thanks and best regards,