DDR output buffer and LVDS pins

Hi guys,

I've got a question. I need to output a gated LVDS clock (I know gated clocks are bad). On my MAX10 FPGA, I was planning on using a DDR buffer configured like this

ddr_output_DUMMY : ddr_output
port map (
outclock => CLK_100M_PLL,
DIN => "01",
pad_out(0) => CLK_O,
ACLR => '0',
oe => Clock_enable
);

However, I cannot connect a DDR output buffer to an LVDS pair of pins. Is this supported on the Cyclone 10 or Arria 10?

Or is there another "clean" way to gate an LVDS output clock?

Regards