Forum Discussion
Benjamin182
New Contributor
New ContributorDDR output buffer and LVDS pins
Hi guys,
I've got a question. I need to output a gated LVDS clock (I know gated clocks are bad). On my MAX10 FPGA, I was planning on using a DDR buffer configured like this ddr_output_DUMMY : d...
EngWei_O_Intel
Frequent Contributor
Frequent ContributorHi there
You may refer to link below to better understanding the implementation and design guideline of clock gating.
Recommended Design Practices, Quartus II Handbook (intel.com)
Thanks.
Benjamin182New Contributor
New ContributorThanks for the reply, but the clock needs to be output from the FPGA to an ADC. And the clock needs to be gated, that's how the ADC is designed.
https://www.analog.com/en/products/ad7961.html
How should I do it with a Max 10 FPGA?
