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Honored Contributor
16 years agoThanks for replying!
The device is sending data at 1 GHz with a 500MHz clock (DDR fashion). I want to split it into 4 streams of 250 MHz inside Arria II GX fpga. I am exploring the suggestion of using alt_dq_dqs but I am not sure if I can provide a high speed clock to a DQS pin in Arria II (I am not sure if DQS pins are also routed to regional or global clock trees) Please advice. Thank!