Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

DDR-II and Arria II Gx

Hi everyone,

I'm trying to implement a DDR-II in an Arria II Gx FPGA along with a standard PCI interface, LVDS connections, etc.

I get the following error message with pin planner :

"Error: Can't find location to place OCT control block "termination_blk0.

Error: Pin termination_blk0~_rup_pad is incompatible with I/O bank 3A. It uses I/O standard 1.8 V, which has VCCIO requirement of 1.8V. That requirement is incompatible with bank's VCCIO setting or other output or bidirectional pins in the bank using VCCIO 3.0V.

How can I get around this problem? Do I have to instantiate directly an OCT block for my DDR-II ? If so, how should I proceed and what tools should I use?

Best regards

1 Reply

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    You should souble check that the RUP and RDN pins do not have any assignments made to them. Since DDR2 uses calibrated termination, those pins are needed to connect the calibration resistors.