DCFIFO - incorrect functionality of a ModelSim timing simulation

Hey guys,

A brief background:My VHDL design (for Stratix III) has input data arriving at 20MHz. The data is read at a rate of 100Mhz. The reading and writing operations aren't necessarily simultaneous. I have prepared a dedicated FIFO block, based on the DCFIFO megafunction, to handle this input interface.

The relevant DCFIFO settings I have chosen:

overflow_checking => "ON" underflow_checking => "ON"

rdsync_delaypipe => 3 wrsync_delaypipe => 3

use_eab => "ON" write_aclr_synch => "ON"

The problem:The block works smoothly in logic simulation (ModelSim 6.5B) and timing (post-synthesis) simulation (Quartus II - 9.1). But, when I run the timing simulation in ModelSim (based on the vho+sdo files generated in Quartus) the functionality is incorrect: The first data sample which is written to the FIFO never appears on the FIFO's output lines. All the following data samples appear correctly.

Each time I raise the write enable, only the second data sample can be read.

Attached:

• A logic simulation in ModelSim (perfect functionality) screen shot.

• A timing simulation in ModelSim (incorrect functionality) screen shot.

purple - writing clock domain. orange - reading clock domain.

fifo_full <-> wrfull fifo_empty <-> rdempty

write_en <-> wrreq read_en = not(fifo_empty) <-> rdreq

I tried (and failed) to solve the problem in the following methods:

• Assigning register on for the input and output ports of the DCFIFO to make sure no setup\hold time violations occur.

• Reading from the FIFO a single clock cycle after fifo_empty goes low.

I am an undergraduate student and a newbie in digital design. This is my final project and it is crucial for me to perform a successful ModelSim timing simulation for the whole design.

I will appreciate any consultation.

Thanks ahead.