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Altera_Forum
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15 years ago

DCFIFO - incorrect functionality of a ModelSim timing simulation

Hey guys, A brief background:My VHDL design (for Stratix III) has input data arriving at 20MHz. The data is read at a rate of 100Mhz. The reading and writing operations aren't necessarily simul...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Did you define all your clocks in Timequest and put all your timing requirements? It could come from bad timing.

I would rely more on Modelsim's output than Quartus'