DCFIFO - incorrect functionality of a ModelSim timing simulation

Hello,

Thank you for answering.

I have defined both of the clocks in the TimeQuest analyzer. Those clocks are to be generated by a single PLL in the top level entity which includes my design as a sub-block. For the simulation's sake, I am generating them in my vhdl test bench. I have no idea how to define the clock uncertainties, so I have set them all to zero. When I perform compilation, only the "Uncosntrained Paths" category of the timing analyzer report goes red.

These are all the timing constraints I have applied. Am I doing anything wrong here ? Am I forgetting something ?

Thanks ahead.