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Altera_Forum
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15 years ago

DCFIFO - incorrect functionality of a ModelSim timing simulation

Hey guys, A brief background:My VHDL design (for Stratix III) has input data arriving at 20MHz. The data is read at a rate of 100Mhz. The reading and writing operations aren't necessarily simul...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

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When I perform compilation, only the "Uncosntrained Paths" category of the timing analyzer report goes red.

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You need to constrain your input/output delays, and then insure that the signals that you generate in your test bench are compliant with those constrains. This is the only way you can ensure that the timing solution will give you realistic results.