Data realignment in StratixII

Hello,

First, you need to receive a predefined pattern from the transmitter device. Next, you put the logic that compares the predefined pattern and lvds receiver output by yourself. The logic should toggle "rx_channel_data_align" signal until it finds pattern matching or aligning the word boundary. Please make sure that "rx_channel_data_aling" is asynchronous signal, so high and low time must be larger than lvds slow clock frequency.

Regards

Hi,gee,

I add a altlvds_rx component and configure it for 1:2 mode. Altlvds_rx is a part of DDR LVDS module which is used connect ADC and FPGA.

(ti's ADC EVM ad62p29 and Arria II fpga EVM)

There isn't 8B10B or other pattern your referred, only odd bit and even bit are alternately come out.

Then what I should do to get the right rx_channel_data_align？

seems to me "rx_channel_data_align" should be a phase shifted lvds clkin.

but I don't know how to get this signal.

Hi smileface,

I didn't check the difference between Stratix II and Arria II, but you don't need to control rx_data_align port when the deserialization factor is 2:1. Maybe you can't make the port enable in the case.

As you mentioned there are only odd and even data. One is clocked rising edge and another: falling edge at transmitter device. If you correctly latch one with rising edge and anotjer with falling edge, there is no ambiguity in data alignment.

In other word, the clock transferred with the data conveys data alignment information in 2:1 serialization mode.

Regards,

hi,gee,

thank you for your reply.

there is another question：when should I open the DPA mode?

usually I use the no DPA.

thanks a lot

alan

Hi smileface,

You need to use DPA only in very high speed, like >500Mbps. You can use it only when you use hard serializer block, which is available serilalizer factor larger than 2.

Regards,