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Altera_Forum
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17 years ago

Data realignment in StratixII

Hi All, The document (Handbook) is not clearly explaining how to use Data Realignment Circutry inorder to align the word boundary. There is no change in the word boundary when i change the prog...
Altera_Forum's avatar
Altera_Forum
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14 years ago

Hi,gee,

I add a altlvds_rx component and configure it for 1:2 mode. Altlvds_rx is a part of DDR LVDS module which is used connect ADC and FPGA.

(ti's ADC EVM ad62p29 and Arria II fpga EVM)

There isn't 8B10B or other pattern your referred, only odd bit and even bit are alternately come out.

Then what I should do to get the right rx_channel_data_align？

seems to me "rx_channel_data_align" should be a phase shifted lvds clkin.

but I don't know how to get this signal.