Forum Discussion
Altera_Forum
Honored Contributor
14 years agoHi smileface,
I didn't check the difference between Stratix II and Arria II, but you don't need to control rx_data_align port when the deserialization factor is 2:1. Maybe you can't make the port enable in the case. As you mentioned there are only odd and even data. One is clocked rising edge and another: falling edge at transmitter device. If you correctly latch one with rising edge and anotjer with falling edge, there is no ambiguity in data alignment. In other word, the clock transferred with the data conveys data alignment information in 2:1 serialization mode. Regards,