Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

CycloneV HPS SDRAM MemoryController pipelined variable waitrequest and readdatavalid

from what i understand, HPS SDRAM Memory Controller can never be non pipelined. simply because your fpga frequency will always be slower than DDR3 IC, this memory controller has to pipeline data to translate it from higher frequency to lower frequency to let the master side(fpga) send and receive data. this takes us to the read data valid and wait request signals; and to the fact that there always will be a variable latency to these signals. so now imagine, that your boss asks you to find out how much data cyclone v transfers to the ddr in every second; if your fpga project has base frequency of 50mhz. what would you answer? you never know when read data valid becomes high. you never know when waitrequest becomes high and how long it stays. these signals always vary in length according to surrounding circumstances... it leaves the impression that pipelined transactions are not designed for strictly timing fixed projects. where, let's say an fpga has to send 2kb every 2us... what if waitrequest stays high for some cycles; then fpga will finish the transfer in 2us + waitrequest cycles. how can it be acceptible to everyone... is there any way to fix waitrequest and readrequest to some fixed number of cycles? i am trying to use cyclone v HPS sdram memory controller

4 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    10 years ago

    The raw timing settings for the DDR are set in the controller registers by the preloader. They are deterministic. However, keep in mind that while your FPGA code is sending/receiving data from SDRAM, the HPS is also fetching instructions, accessing variables, the stack, etc. DMA from USB, Ethernet, etc may also be happening. There are multiple things using that memory at the same time. If you need deterministic timing, add a dedicated DDR3 for the FPGA and use one of the DDR controllers on the FPGA side. That memory isn't being used by the HPS and timing will be under control of the FPGA code.

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    10 years ago

    i have a single register connected to memory controller from fpga nothing else tries to access memory. let's say you issue a read request command; how many cycles will it need to answer readdatavalid..? is needed cycle count value written in the HPS control registers? i found refresh interval value in control registers but could not find anything related to readdatavalid or waitrequest. changing cas latency value in control registers does not have any effect...

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    10 years ago

    --- Quote Start ---

    let's say you issue a read request command; how many cycles will it need to answer readdatavalid..?

    --- Quote End ---

    Well, it's variable latency, that's why it uses readdatavalid :) The exact number of cycles depends on the internal state of the DDR chip. For example if you try to read a single word after a reset or refresh, the latency will be the highest ("RAS+CAS+burst_length+controller_pipeline" cycles). Subsequent reads might return faster if they are from addresses within the same burst block (as they are cached in the controller already), or within the same SDRAM row (as we do not need to wait for the RAS cycles). Assuming the master is fully pipelined, the overall throughput depends on your application access profile, for example you get better read/write performance if you move large blocks of data which access the SDRAM sequentially (for example a streaming application like reading an image file or a movie file), and worse performance if you perform many random accesses which force the SDRAM controller to constantly close/open rows. SDRAM devices themselves are pipelined, and non-pipelined or non-latency aware masters will not be able to get adequate use of the SDRAM design.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    10 years ago

    Yes, the effects crush and I discuss combine to make it impractical to calculate an exact latency for memory accesses. When you combine waits for something else using memory and the variable latency of DDR etc, you can get quite a wide range. I'd suggest creating a typical load for your application and have your FPGA module keep track of min/typ/max latencies.