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Altera_Forum
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11 years ago

CycloneV HPS SDRAM MemoryController pipelined variable waitrequest and readdatavalid

from what i understand, HPS SDRAM Memory Controller can never be non pipelined. simply because your fpga frequency will always be slower than DDR3 IC, this memory controller has to pipeline data to t...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

i have a single register connected to memory controller from fpga nothing else tries to access memory. let's say you issue a read request command; how many cycles will it need to answer readdatavalid..? is needed cycle count value written in the HPS control registers? i found refresh interval value in control registers but could not find anything related to readdatavalid or waitrequest. changing cas latency value in control registers does not have any effect...