--- Quote Start ---
let's say you issue a read request command; how many cycles will it need to answer readdatavalid..?
--- Quote End ---
Well, it's
variable latency, that's why it uses readdatavalid :) The exact number of cycles depends on the internal state of the DDR chip. For example if you try to read a single word after a reset or refresh, the latency will be the highest ("RAS+CAS+burst_length+controller_pipeline" cycles). Subsequent reads might return faster if they are from addresses within the same burst block (as they are cached in the controller already), or within the same SDRAM row (as we do not need to wait for the RAS cycles). Assuming the master is fully pipelined, the overall throughput depends on your application access profile, for example you get better read/write performance if you move large blocks of data which access the SDRAM sequentially (for example a streaming application like reading an image file or a movie file), and worse performance if you perform many random accesses which force the SDRAM controller to constantly close/open rows. SDRAM devices themselves are pipelined, and non-pipelined or non-latency aware masters will not be able to get adequate use of the SDRAM design.
Honored Contributor
