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Altera_Forum
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11 years ago

CycloneV HPS SDRAM MemoryController pipelined variable waitrequest and readdatavalid

from what i understand, HPS SDRAM Memory Controller can never be non pipelined. simply because your fpga frequency will always be slower than DDR3 IC, this memory controller has to pipeline data to t...
Altera_Forum's avatar
Altera_Forum
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11 years ago

The raw timing settings for the DDR are set in the controller registers by the preloader. They are deterministic. However, keep in mind that while your FPGA code is sending/receiving data from SDRAM, the HPS is also fetching instructions, accessing variables, the stack, etc. DMA from USB, Ethernet, etc may also be happening. There are multiple things using that memory at the same time. If you need deterministic timing, add a dedicated DDR3 for the FPGA and use one of the DDR controllers on the FPGA side. That memory isn't being used by the HPS and timing will be under control of the FPGA code.