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Altera_Forum
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11 years ago

CycloneV HPS SDRAM MemoryController pipelined variable waitrequest and readdatavalid

from what i understand, HPS SDRAM Memory Controller can never be non pipelined. simply because your fpga frequency will always be slower than DDR3 IC, this memory controller has to pipeline data to t...
Altera_Forum's avatar
Altera_Forum
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11 years ago

Yes, the effects crush and I discuss combine to make it impractical to calculate an exact latency for memory accesses. When you combine waits for something else using memory and the variable latency of DDR etc, you can get quite a wide range. I'd suggest creating a typical load for your application and have your FPGA module keep track of min/typ/max latencies.