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Honored ContributorCyclone3 Power Up level doesn't work
A design with an EP3C40F324I7 has the pin U18 as an registered output.
This pin is used to control another dcdc's nSHDN (Shutdown negativ logic) The fpga is configured via epcs. this dcdc is under control of a custom ip and is only powered up when needed as this is a battery powered design. During power up, as soon as the voltages are stable the pin goes to high and the dcdc starts. the fpga gets its configuration from the epcs. when the configuration is done the pin goes to low as this is the default level of this pin. i want that this pin is low after power up until the custom ip sets it to high to enable the dcdc. this is done as soon as the fpga is in user mode but not during configuration. The pin U18 is a Column IO and the PLL4_CLKOUTp. Quartus has an option Power Up Level and it is used as set_location_assignment PIN_U18 -to 3VEnable set_instance_assignment -name POWER_UP_LEVEL LOW -to 3VEnable But this does not help. Quartus reports Warning: Pin "3VEnable" has no register for Power-Up Level option but this is my verilog code sniped reg Enable_3V; always @ ( posedge gls_clk or negedge gls_reset_n ) if ( !gls_reset_n ) Enable_3V <= 1'b0; the register Enable_3V goes to top level and there it is connected to output pin 3VEnable if i am not wrong, then this is a register but why does quartus think it is not a register ? But more important how can i force my pin to low during power up. please notice that there is a pull down on that pin. it is a resistor devider 100k + 560k with a 47nF cap in parallel to the 560k. this will give ~2,5v maximum and a smooth softstart to reduce the startup durrent. any ideas ? thanks in advance. Michael EDIT : it is Pin U1815 Replies
Altera_ForumThe 2k pull down is the only way I know to be sure that the signal will be 0 during power up.
You could try to put a low pass filter after the pull down and write a small PWM generator in VHDL to create a slow ramp up on the output pin. Just an idea...- Altera_Forum
@Daixiwen
The datasheet http://www.altera.com/literature/hb/cyc3/cyc3_ciii52001.pdf says on page 9 table 1-10 pull up min 7k @ 3V page 10 part 2 of 2 for this table pull down min 6k @ 3V so it must be possible as the parameter says "Value of I/O pin pull-down resistor before and during configuration" and thats what i am looking for. enabling this pull down to set this pin to 0 until user mode is entered. but i guess you are right as note 1 for this table says that the pull down feature is only available for JTAG TCK :-( @ Jake i tried different ways //verilog 1995 reg Enable_3V /* synthesis altera_attribute = "-name POWER_UP_LEVEL LOW" */; // Verilog 2001 (* altera_attribute = "-name POWER_UP_LEVEL LOW" *) reg Enable_3V; as well as reg Enable_3V = 1'b0; but none of them works. between power on and until the fpga starts to work in user mode the pin is 1 as soon as the user mode is reached, this pin goes to 0 so it seems that it is realy impossible ... i can't go to 2k pull down as this will disable the soft start function of the dcdc - Altera_Forum
You can't force the pin to stay low before the user mode. All the pins are set to weak pull-up during configuration an no settings in the Quartus project will change that, for the simple reason that until the configuration is loaded the FPGA doesn't know what to do with his pins yet.
The only solution is to put an external pull down on the PCB. Check the internal weak pull-up value in the Cyclone III datasheet, because it's not as weak as that. As an example for a 3.3V I/O the "weak" pull-up can be as low as 7k, and you need to put an external pull down of 2k or less to guarantee a voltage under 0.8V during power up. - Altera_Forum
See the first example on page 9-68 of this document:
http://www.altera.com/literature/hb/qts/qts_qii51008.pdf Jake - Altera_Forum
You need to make the assignment on the register instead of the pin. You can either do this using the assignment editor or with a Verilog attribute in the code.
Jake
