Cyclone3 Power Up level doesn't work

@Daixiwen

The datasheet

http://www.altera.com/literature/hb/cyc3/cyc3_ciii52001.pdf

says on page 9 table 1-10 pull up min 7k @ 3V

page 10 part 2 of 2 for this table pull down min 6k @ 3V

so it must be possible as the parameter says "Value of I/O pin pull-down resistor before and during configuration" and thats what i am looking for. enabling this pull down to set this pin to 0 until user mode is entered.

but i guess you are right as note 1 for this table says that the pull down feature is only available for JTAG TCK :-(

@ Jake

i tried different ways

//verilog 1995

reg Enable_3V /* synthesis altera_attribute = "-name POWER_UP_LEVEL LOW" */;

// Verilog 2001

(* altera_attribute = "-name POWER_UP_LEVEL LOW" *) reg Enable_3V;

as well as

reg Enable_3V = 1'b0;

but none of them works.

between power on and until the fpga starts to work in user mode the pin is 1

as soon as the user mode is reached, this pin goes to 0

so it seems that it is realy impossible ...

i can't go to 2k pull down as this will disable the soft start function of the dcdc