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Altera_Forum
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17 years ago

Cyclone3 Power Up level doesn't work

A design with an EP3C40F324I7 has the pin U18 as an registered output. This pin is used to control another dcdc's nSHDN (Shutdown negativ logic) The fpga is configured via epcs. this dcdc is ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

The 2k pull down is the only way I know to be sure that the signal will be 0 during power up.

You could try to put a low pass filter after the pull down and write a small PWM generator in VHDL to create a slow ramp up on the output pin.

Just an idea...