Cyclone3-Overshoot/Undershoot

Hi,

After PCB Design CIII – EP3C40 based board, in the post routing SI Simulation we are getting some overshoots and undershoots in DDR Signals and LVDS (As receiver) signals. As we are using DDR1 so all VCCIO pins of the banks dedicated for DDR along with the VCCIO pins of the banks dedicated LVDS are connected to 2.5V. In worst case we are getting the overshot/undershoot of 350mV near the FPGA pins i.e. at the FPGA pin we are getting 2.85V and -0.35V overshot and undershoot respectively.

In the Table 1–12 [Single-Ended I/O Standard Specifications] of Cyclone3 Handbook the Minimum value of VIL and Maximum value of VIH is given as -0.3 and VCCIO+0.3V respectively. Where as in Table 1–2Maximum Allowed Overshoot Voltage is defined as 3.95V for 100% and for under shoot it is said that it can go up to –2.0 V for input currents less than 100 mA and for periods shorter than 20 ns.

Can any one clarify if the VCCIO Pin is connected to 2.5V then up to what voltage level the Undershoot and Overshoot is permissible if the duration of these Overshoot/undershoot is less than 5nS.

In our board, we are using the FPGA as LVDS receiver only. So for SI Analysis we replaced the LVDS connector with 2nd Cyclone3 IBIS Model and used it as a LVDS Transmitter. In that case we are getting the overshoot/Undershoot of 600mV at the pins of Cyclone3 which is a LVDS receiver. Can any one clarify is this overshoot/Undershoot of 600mV is permissible?

In actual the LVDS signal is supposed to come from a 3.3V LVDS Transmitter. Where as, to use the Cyclone3 as LVDS receiver, the corresponding VCCIO is required to be connected to 2.5V. Please clarify whether this design is going to damage the Cyclone3 device?

Regards,

S. Sarkar