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Altera_Forum
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18 years ago

Cyclone3-Overshoot/Undershoot

Hi, After PCB Design CIII – EP3C40 based board, in the post routing SI Simulation we are getting some overshoots and undershoots in DDR Signals and LVDS (As receiver) signals. As we are using DDR1 s...
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Altera_Forum
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18 years ago

Hello FvM,

Thanks for your comments on the waveforms. Because of space constraints we had to place the termination resistors a little far away from the FPGA. The average trace length between the Termination Resistor and the FPGA pin is approx 1000 mils. I am attaching the Gerber Files in PDF format in the forum. You are kindly requested to give a look and suggest any better solution if possible for the improvement of the signals.

Regards,

S Sarkar