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Altera_Forum
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18 years ago

Cyclone3-Overshoot/Undershoot

Hi, After PCB Design CIII – EP3C40 based board, in the post routing SI Simulation we are getting some overshoots and undershoots in DDR Signals and LVDS (As receiver) signals. As we are using DDR1 s...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
18 years ago

The RAM signals look quiet good, compared to some waveforms shown in Altera applications note. If they verify in real life, I would be happy. With terminated SSTL I/O standards you should mainly think about correct RAM operation rather than exceeding maximum ratings.

The LVDS waveforms may not endanger the CIII parts (most likely), but they show incorrect levels anyway. You seem to have forgotten the 100 ohm terminating resistors at the receiver. A correct lvDS signal has a much lower voltage variation, around a common mode level of about 1.2V. With termination resistors, the overshoot will be gone.