Forum Discussion

UF1's avatar
UF1
Icon for New Contributor rankNew Contributor
2 years ago

Cyclone10LP SEU CRC error implementation (part 2)

Dear support team, I open a new post as the first has been closed without an answer, only references to already read documentation . We have enabled the CRC_ERROR pin and we want to instantiate...
Configuration
Farabi's avatar
Farabi
Icon for Regular Contributor rankRegular Contributor
1 year ago

Hello,


Can you try this VHDL?

-----------

i_cyclone10lp_crcblock : cyclone10lp_crcblock


generic map (


oscillator_divider => 1)


port map (


clk => '0',


shiftnld => '1',


crcerror => s_altcrc_crcerror,


regout => open);


-------------

regards,

Farabi


UF1's avatar
UF1
Icon for New Contributor rankNew Contributor
1 year ago

Farabi,

It doesn't work out.

The IP cyclone10lp_crcblock isn't instantiated in Quartus whereas it is under modelsim.

The IP cyclone10lp_crcblock doesn't appear in the IP catalog (Quartus 22.1).

I have tried to include the following library :

library cyclone10lp;
use cyclone10lp.cyclone10lp_components.all;

Any suggestion ?

Regards,

GB

2.15.0.0