Cyclone10LP SEU CRC error implementation (part 2)

Hello Farabi,

I can't share you the whole project but attached is the VHDL file of IP instantiated at the top. I use signaltap to visualize the output of the of cyclone10lp_crcblock.

> Is your design following this guide? link : https://www.intel.com/content/www/us/en/docs/programmable/683777/current/accessing-error-detection-block-through.html

Yes, I followed this guide and read the documentation of the handbook (ID 683777) chapter 7 "Seu mitigation in Intel Cyclone10 LP Devices". We use the device Cyclone 10 LP 10CL120YF484I7G.

Thanks for your support,

GB