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LTN's avatar
LTN
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4 years ago

Cyclone10 GX: About Cyclone10GX Transceiver Native PHY.

Hi Intel, When I am learning to use SFP+ interface of Cyclone 10 GX board, I designed the project with ATXPLL IP core、Reset Controller IP Core 、Cyclone 10 GX Transceiver Native PHY, and connected t...
RichardT_altera's avatar
RichardT_altera
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4 years ago

Hi @LTN

in the previous reply I stated the following

“Simulated one of the designs and saw the same behaviour that you describe. Could you try to enable the dynamic reconfiguration interface on the PHY, and ensure that the reconfig_clk is driven (same CLK as the Reset Controller should be OK), Please also ensure that the reconfig_reset input port gets a power on reset. When I did this it fixed my problem here.”

The screenshots you provided do not show the Avalon Memory Mapped interface dynamic reconfiguration port clock or reset.