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Re: Cyclone10 GX: About Cyclone10GX Transceiver Native PHY.
Hi @RichardTanSY_Altera , The problem I face are same as the beginning. Now I can check the tx_serial_clk0,it's working in 5156.25MHz.But the tx_clkout and the rx_clkout signal is still always '0'.I have been working on this for such a long time but there is still no solution. I compared my project like the example you posted carefully,checked every link of PHY,reset control,andATX PLL.I am new to VHDL,maybe I didn't get the exact meaning of the example,which bothered me a lot. Please help me... Thanks very much. Best Regards, LiRe: Cyclone10 GX: About Cyclone10GX Transceiver Native PHY.
Hi @RichardTanSY_Altera, There is my project in QuartusPro 17.1. In this project, I enable the dynamic reconfiguration interface on the PHY, and set these interface like the example. Then simulate the project in ModelsimStarterEdition. The current problem remains that the tx_clkout and the rx_clkout signal is always 0.And after enable the reconfiguration interface,most of the signals are working in a wrong way now. By the way, as you said,I post other question in a new case,why never recive any reply? Regards, Li.Re: Cyclone10 GX: About Cyclone10GX Transceiver Native PHY.
Hi @RichardTanSY_Altera , I have downloaded Quartus Pro 19.1 and compared the example with my project.Then i modified its parameter like the example.But i didn't get what i want,only get this: Do you know what's wrong with my project? Thanks, LiClock Generation Block of Cyclone10GX Native PHY.
Hi Intel, When I try to use the Native PHY IP Core in Quartus Pro 19.1, I choose the 10GBASE-R reset. I read the user guide of this ip core,in "2.6.2 10GBASE-R and 10GBASE-R with IEEE 1588v2 Variants" it describes the Clock Generation Block like this: Could you tell me where do the three Serial clocks come from? Then, I use the ATX PLL to generate a clock in 5156.25MHz, and link it to PHY, but CGB did not generate tx_clkout and rx_clkout as expected,do you know why? Thanks, Li.Re: Cyclone10 GX: About Cyclone10GX Transceiver Native PHY.
Hi @RichardTanSY_Altera , I downloaded QuartusPro 19.1 and compared the example with mine, now i know what's the difference between them. In my project, i used the"10GBASE-R" preset of Native PHY IP Core, but the example didn't.Now i am trying to create another project like the example in verilog to simulate it. By the way, Merry Christmas~ Best regards, Li.Re: Cyclone10 GX: About Cyclone10GX Transceiver Native PHY.
Hi @RichardTanSY_Altera , I tried to simulate your example in QuartusPro 17.1,but I failed in the compile step.And I find the ip in that project maybe is generated by Pro 19.1? So I can't check it's parameter either. Sorry,next time I will file a new post for the other questions. Li.Re: Get problem while use the qts_pcie_sfp and the qts_fmc demo of C10GFP
Hi, I didn't make any change with qts_pcie_sfp_17_1_compile_ok.qar project,in Quartus Pro 17.0. That two demo could compile successfully, but when I what to check the details of it's ip parameter, I find there are some missing modules.It's so puzzling. I haven't tried the other demos yet. LiRe: Cyclone10 GX: About Cyclone10GX Transceiver Native PHY.
Hi @RichardTanSY_Altera , Thanks very much for your reply, I find which lib is needed, and simulated the project successfully.This time i can show you the wave of reconfigurated Native PHY: We can find that the wave of tx_clkout and rx_clkout is still wrong.What are the possible causes? After reading the user guide(2.6.2 10GBASE-R),I think maybe the CGB of PHY isn't work(or maybe the PHY isn't work).The other question is that where do the there serial_clock sources come from?And how does the Clock Divider work? Regards, Li.Re: Cyclone10 GX: About Cyclone10GX Transceiver Native PHY.
Hi @RichardTanSY_Altera , I read the dynamic reconfiguration part of the user guide again, and realize that dynamic reconfiguration is related to Avalon-MM interface.Is the Avalon-MM interface necessary? Looking forward to your reply. Regards, Li.
