Cyclone10 GX: About Cyclone10GX Transceiver Native PHY.

Have you try to simulate the design example that was provided previously and compared it with yours?

For other unique question, please kindly file a new case. This will helps with our case analysis that we use to assess our customer support requirements. Hope you understands.

Hi @RichardTanSY_Altera ,

I tried to simulate your example in QuartusPro 17.1,but I failed in the compile step.And I find the ip in that project maybe is generated by Pro 19.1? So I can't check it's parameter either.

Sorry,next time I will file a new post for the other questions.

Li.

Hi @RichardTanSY_Altera ,

I downloaded QuartusPro 19.1 and compared the example with mine, now i know what's the difference between them. In my project, i used the"10GBASE-R" preset of Native PHY IP Core, but the example didn't.Now i am trying to create another project like the example in verilog to simulate it.

By the way, Merry Christmas~

Best regards,

Li.

Hi @RichardTanSY_Altera ,

I have downloaded Quartus Pro 19.1 and compared the example with my project.Then i modified its parameter like the example.But i didn't get what i want,only get this:

Do you know what's wrong with my project?

Thanks,

Li

Hi @LTN

May I know what is the current problem that you are facing?

Could you help to share your whole design and the screenshot (with better resolution)?

Somehow the screenshot attached in the forum is in low resolution so it does not help.

Best Regards,

Richard Tan

Hi @RichardTanSY_Altera ,

The problem I face are same as the beginning. Now I can check the tx_serial_clk0,it's working in 5156.25MHz.But the tx_clkout and the rx_clkout signal is still always '0'.I have been working on this for such a long time but there is still no solution.

I compared my project like the example you posted carefully,checked every link of PHY,reset control,andATX PLL.I am new to VHDL,maybe I didn't get the exact meaning of the example,which bothered me a lot.

Please help me...

Thanks very much.

Best Regards,

Li

Hi @LTN

in the previous reply I stated the following

“Simulated one of the designs and saw the same behaviour that you describe. Could you try to enable the dynamic reconfiguration interface on the PHY, and ensure that the reconfig_clk is driven (same CLK as the Reset Controller should be OK), Please also ensure that the reconfig_reset input port gets a power on reset. When I did this it fixed my problem here.”

The screenshots you provided do not show the Avalon Memory Mapped interface dynamic reconfiguration port clock or reset.

Hi @RichardTanSY_Altera ,

Here it is.

Hi @LTN

May I know does my latest reply helps?

Do you need further help in regards to this case?

Best Regards,
Richard Tan

p/s: If any answer from the community or Intel support are helpful, please feel free to give Kudos.

Hi @LTN

I took the design and generated the simulation models for the IP and I notice that these options were not selected by default. Is it possible that you are trying to simulate the design with the synthesis RTL? You cant do that.

I hacked my simple testbench and simulated your project with it. As you can see it works just fine. I’ve attached the project with my testbench back to you.

Best Regards,
Richard Tan

p/s: If any answer from the community or Intel support are helpful, please feel free to give Kudos.

I have yet to receive any response from you to the previous question/reply/answer that I have provided but I believed that I have answered your question.
With that, I will now transition this thread to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.

Best Regards,
Richard Tan

p/s: If any answer from the community or Intel support are helpful, please feel free to give Kudos.