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LTN's avatar
LTN
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4 years ago

Cyclone10 GX: About Cyclone10GX Transceiver Native PHY.

Hi Intel, When I am learning to use SFP+ interface of Cyclone 10 GX board, I designed the project with ATXPLL IP core、Reset Controller IP Core 、Cyclone 10 GX Transceiver Native PHY, and connected t...
RichardT_altera's avatar
RichardT_altera
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4 years ago

Hi @LTN

I’ve had a quick look art the design and I would perhaps change the source of the CLKUSR to be a general purpose CLK pin.

You should be able to observe the tx_serial_clk. Are you saying that it is 0, or are you saying that you cant see it at all? If it is 0, this suggests that perhaps the TX PLL is in reset. The same goes for the rx_clkout, if that is 0, then perhaps the PHY is in reset.

What are the status of all of the Reset Controller IP reset signals? Perhaps it would be easier if you showed me what the signals are doing.

The other obvious thing is that the CDR will not lock unless there is incoming data so you should of course ensure that your testbench implements a loopback between the tx_serial and rx_serial ports.

All things being good, I’d also ensure that you simulate for at least 20us.

Best Regards,
Richard Tan

p/s: If any answer from the community or Intel support are helpful, please feel free to give Kudos.

LTN's avatar
LTN
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4 years ago

Hi @RichardTanSY_Altera ,

Thanks for your reply.

  1. First, about the CLKUSR,I haven't try this way up to now,but I will try as you said later.
  2. About the signals. I can't observe the tx_serial_clk , the reason is in the following post:Cyclone10GX:about ATX PLL IP Core.But in simulation I can observe the wave of pll_locked, and I will show it in attachment,I think this signal is working as I expected. So as the tx_clkout and the rx_clkout, I can observe them but they are all 0, I don't know why.
  3. About the Reset Controller IP reset signals, I can show you as following:
  4. About the loopback between the tx_serial and rx_serial ports.I accept your advise and connect the two signals together like this:

    But due to the previous problem, these signals are 0 all the time.

  5. After simulating at least 20us,I get the result like this:>5000us

Regards,

Li.

  • RichardT_altera's avatar
    RichardT_altera
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    4 years ago

    Hi @LTN

    The CDR needs toggling RX data in order for it to lock to data. For this to happen you of course need toggling data on the TX serial line (if running in loopback). Right now you don’t have toggling TX serial data because your tx_parallel_data is static 0. I need to understand why your TX_CLKOUT isn’t toggling though.

    Can you please show the behaviour of the signals on the PHY IP and Reset Controller IP instead of the top level ports?

    Regarding the tx_serial_clk,:Cyclone10GX:about ATX PLL IP Core. You need to consider that the fast transceiver signals do not go through the FPGA PLD fabric. So you cant use Signaltap because that is in the FPGA fabric. Simualtion is fine though because you can look anywhere.

    Best Regards,

    Richard Tan

    • LTN's avatar
      LTN
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      4 years ago

      Hi @RichardTanSY_Altera ,

      I don't understand what do you mean by"show the behaviour of the signals on the PHY IP and Reser Controller IP",do you mean the definition and function of them? If you mean this I can show you the user guide of these three IP Core-in one PDF which is downloaded from Intel:Intel Cyclone 10 GX Transceiver PHY User Guide, I hope this could help you find why TX_CLKOUT isn’t toggling.

      By the way,this is the first I've heard of Signaltap, now I am going to learn to use it.

      Thanks a lot,

      Li.

      • RichardT_altera's avatar
        RichardT_altera
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        4 years ago

        Hi @LTN


        I am not referring to the user guide.

        Currently you are showing signals in the input and output ports of the top level. I’d like to see the actual behaviour of the signals on the PHY, TX PLL, and Reset Controller IP instances.