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Honored ContributorCyclone V won't configure via active serial
I have a Cyclone V design (5CSEBA5) that I am trying to configure using a EPCQ128 device
I have created a .sof file that I can load into the FPGA directly (Jtag USB Blaster) and it works fine (blinks my user debug LED) I have tried to take that same .sof file and create the file to program the EPCQ128, but I am not sure I am going about this the right way. I used the "Convert programming file" program with the following settings Programming File Type = Jtag Indirect Configuration file Configuration device = EPCQ128 Mode = Active Serial x 4 File name = output_fille.jic create memory file and create config data boxes are NOT checked under "input files to convert" there are: Flash Loader 5CEBA5 SOF Data romulus.sof The romulus.sof file is the same one that I can load directly and get my blinking LED I generate the file, then use the stand alone programmer. I autodetect the FPGA, then "attach" the EPCQ128 In the box for assigning the files I select the EPCQ128 and "change" the file (I discovered that you MUST change the file, not "add"!) to point to the jic file just created. I check the box for programming the EPCQ128 and click start. The FPGA programs with the "factory default SLF" image and the it erases and programs the EPCQ128. I can verify the EPQC128, so everything looks okay. But then I power cycle and expect the FPGA to configure from the flash device, but it fails. I have the MSEL[4:0] pins set to 10011 (standard active serial). I have also tried 10010, for FAST AS. I can probe the pins on the EPCQ128 and I see: DCLK is going at about 80 MHz. nCSO is mostly low, with a short pulse high every 175ms The four data pins are toggling The nCE pin to the FPGA is tied low NCONFIG and NSTATUS are pulled high (10K) - (addition: Nstatus does get asserted low every 175 ms) Config_done drives a FET which in turn drives an LED. This circuit works as expected when I program the FPGA directly via JTAG I figure that the basic JTAG connection to the FPGA is okay as I can configure it directly and it appears I can program the FLASH device through it. The connections between the FPGA and serial FLASH device appears to be proper because I can program and verify the FLASH I am suspecting that I didn't create the .jic file properly but I don't know what to do different. I am using a .jic file because that is the only format that the programmer will allow me to select for the file that will get programmed into the attached flash device. I would really appreciate any help here! Rod12 Replies
Altera_ForumIf you can configure your device via JTAG then there is no problem with any of the device's configuration pins - nCONFIG, nSTATUS, nCE, CONF_DONE, INIT_DONE. So, you can ignore these.
I suspect, like you, you're creating your .jic file incorrectly. Refer to "how do i create a jtag indirect configuration file (.jic) file with my nios ii hardware and software image? (https://www.altera.com/support/support-resources/knowledge-base/solutions/rd10132010_126.html)". You can ignore steps 1 to 3 and 11, they're required if you want to boot your Nios software from EPCS too. Start at line 4. Ignore the references to map & hex files in step 12. You should then be able to select your .jic file from within the Quartus programmer and configure your device. Cheers, Alex- Altera_ForumHi Rod, Try with below options Tick memory file check box while generating .jic file.(To generate output_file.map) The .map file contains starting and ending addresses for boot code, configuration page data, and application code. Or 1.Check the pin nConfig and nStatus in reset state it should be high state. 2.Is it development board/custom board?
- If it is custom board: Do you have any hardware/IC in path on nSTATUS and CONF_DONE (like line driver / TRX).
