Hello. I am new to Cyclone V. I took my design for Cyclone III and recompiled it with Quartus II web 13.1. From the timing analyzer, I can see that the maximum clock rate is only 84 Mhz while I was getting 131 Mhz with cyclone III at the same C8N speed grade. The timing recommendation is incomprehensible. Would anyone who knows cyclone V well tell me if this is expected? Is Cyclone V significantly slower than Cyclone III? This doesn't make sense. Thanks a lot. Jixiang

Move to a later version of Quartus (15.0) The timing models were not final in Quartus 13.1 for Cyclone V and were very conservative (overly so). You should see much improved timing performance in Quartus 15.0. Pete

Thanks Pete. I have done just that. The speed does improved to 88 Mhz. However, it's still significantly slower than Cyclone III or Cyclone IV which I get comparable performance.https://www.alteraforum.com/forum/attachment.php?attachmentid=10792

Ok that sounds wrong. I expect a significant increase in performance for Cyclone V from Cyclone III. My guess is there are some false paths that are getting ignored in the conversion, (IE the PLL Changed, so the old SDF file isn't valid anymore). I would look at that. If you can send a timing report for both the designs we can look at it. Pete

Cyclone V is of much newer technology as compare to the Cyclone III. Thus, we should expect generation V to have much better performance than Cyclone III. As mentioned by anakha, I believe we might need to further look into the timing constraints to see if there is any anomaly.

That's a good news because I do plan to move all to Cyclone V and the performance is important. I do not seem to find a way to generate a timing report file. I opened the timeQuest analyzer and I see that I can write a SDC file but that isn't a timing report, is it? Thanks in advance. Jixiang

Cyclone V speed is much slower | Altera Community

34 Replies

Altera_Forum
Honored Contributor
10 years ago
Hi Pete;

I've been playing with the PLL settings in qsys this morning, but so far can't find any setting that reduces the reported clock delay. Changing to source synchronous mode actually increased the reported clock delay to 5.7ns. From the PLL documents it sounds like normal mode should do the trick, but no luck there.

I haven't tried zero delay buffer yet since I don't have a clock output to connect to.
Altera_Forum
Honored Contributor
10 years ago
Quartus synthesis might be able to achieve a higher maximum clock speed if the design is constrained for it. Did you try?
Altera_Forum
Honored Contributor
10 years ago
Yes, I think I've got the constraints right. The problem is that Quartus can't make the timing constraints on the Cyclone 5 while the identical project using a Cyclone 4 meets timing with no problems.

I've got a service request in with Altera now, so I'll post back if I can get to the bottom of this.

Thanks,
Steve
Altera_Forum
Honored Contributor
10 years ago
So I heard back from Altera support on this. It looks like the long clock delays are a fact of life on the Cyclone-V. To quote Altera support:

"Since the clock network structure of Cyclone V is different than the old device, we will expect a longer delay in the clock path."

I'm experimenting now with manually phase shifting the PLL to try to improve my timing, but it's a bit disappointing to find that the Cyclone-5 has so much more delay on it's clock network then the Cyclone-3 or 4 devices.

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Cyclone V speed is much slower

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