Forum Discussion
Altera_Forum
Honored Contributor
10 years agoHi Pete;
I've been playing with the PLL settings in qsys this morning, but so far can't find any setting that reduces the reported clock delay. Changing to source synchronous mode actually increased the reported clock delay to 5.7ns. From the PLL documents it sounds like normal mode should do the trick, but no luck there. I haven't tried zero delay buffer yet since I don't have a clock output to connect to.