Forum Discussion
BrianSune_Froum
Contributor
ContributorCyclone V SoC family HPS EMI device support
Dear Intel and all, According to emi_ip-683841-666668.pdf "4.3. SDRAM Controller Memory Options Bank selects, and row and column address lines can be configured to work with SDRAMs of various tec...
Hi brian8sune,
Using the memory component with 2K page size should be okay.
But you cannot implement the interface as DQx16bit since the IP only allow for DQx8bit configuration.
Therefore, you need to route the memory as 8 DQ bit per DQS group.
Regards,
Adzim
AdzimZM_Altera
Regular Contributor
Regular ContributorHi brian8sune,
Using the memory component with 2K page size should be okay.
But you cannot implement the interface as DQx16bit since the IP only allow for DQx8bit configuration.
Therefore, you need to route the memory as 8 DQ bit per DQS group.
Regards,
Adzim
BrianSune_FroumContributor
ContributorHi Adzim,
Of cause, for DDR3 always route in byte form with DS/DM/DSQ group byte data bit swap allowed.
So I guess this is settle and clear thank you
